A non-volatile memory cell, such as a flash memory cell, with multiple floating gates to store multiple bits of data is known. Such a memory cell generally includes two floating gates to store two bits of data, and each bit of datum may be stored (programmed) and read individually. U.S. Pat. No. 5,929,480 describes a non-volatile semiconductor memory device having first and second floating gates. However, due to the complexity of some of the known dual-storage memory cell structures, these memory cells cannot be easily scaled, which presents a major obstacle to commercialization. Furthermore, the methods for manufacturing these conventional dual-storage memory cells are complicated and costly. Therefore, there is a need for a dual-storage memory cell with excellent scalability and may be manufactured using existing CMOS technology to minimize cost.